It is desirable to make transistors as small as possible so that more can be put on a given size integrated circuit die. This allows ever more complex circuits to be made and more economically as line widths decrease.
CMOS transistors have encountered difficulties lately as line widths and design rules have shrunken to the sub-100 nanometer region, such as to 45-nanometer and smaller line widths and design rules. Some CMOS problems have to do with excessively high static power consumption when the CMOS pair is not switching and there should not be any power consumed. This problem arises at least in part from short channel effects which become more pronounced as line widths decrease.
One attempted solution to this problem has taken the form of Junction Field Effect Transistors (JFET) with doping profiles controlled so as to make the transistor operate in enhancement mode so that it has essentially zero drain current at zero gate bias. These JFET devices can be made at 45 nanometer or smaller line widths.
Speed of operation in switching transistors depends upon the amount of drain current since parasitic and load capacitances coupled to the drain need to be charged and discharged as switching occurs. This charging and discharging changes the voltage on these capacitors to switch transistors on and off. Therefore, larger drain currents allow transistors to operate and switch at higher frequencies. Recently, multi-gate transistors (e.g., double gate, tri-gate, and the like) have been proven to provide such benefits. In a multi-gate device, the channel is surrounded by multiple gates thus allowing improved suppression of off-state leakage current and enhancement of the on-current.
For example, in a Junction Field Effect transistor (JFET), a multi-gate (e.g., double gate) configuration allows enhanced modulation of the depletion region when the gate bias is changed by increasing the volume of the channel depletion that can be modified by the gate. Thus, generally, a double-gate JFET has a faster switching time compared to a single-gate JFET due to a number of factors, one of which includes increased drain current (on-current) from, for example, reduced channel resistance due to decreased channel depletion for the same gate bias.
For JFETs, to control the bias applied to each of the front gate and back gate, separate surface contacts for the front gate and back gate are generally utilized. This double-gate configuration often further necessitates a surface metal interconnect to connect the front gate and back gate contacts.
However, the surface contact to the back gate consumes additional area thus potentially impacting scalability of double-gate devices. For example, the size of the back gate surface contact must typically be large enough to prevent misalignment errors associated with various masks. It is also desirable to make transistors as small as possible so that more can be put on a given size integrated circuit die. This allows ever more complex circuits to be made and more economically as line widths decrease.
There therefore remains a need for a novel double-gate device structure that is not penalized by larger size or area consumption or occupation of the double-gate device as compared to an area size consumed or occupied by a single-gate device and that reduces parasitic capacitance and increases switching speed, especially for sub 100-nanometer line width devices.